The performance, density, and cost of integrated circuit (IC) chips have been improving consistently and continuously. Much of the improvement has been due to the ability to scale transistors to increasingly smaller dimensions, resulting in higher speed and higher functional density. The continued shrinking of transistor sizes on the IC chips, however, poses many challenges to metal interconnect technology. For instance, as interconnects get thinner and distances between interconnects shrink, resistance and inter-metal capacitance rise. By changing to different materials, i.e. higher conductivity material for the metal lines and lower permittivity (low-k) dielectrics for the insulating material, device geometry can continue to shrink without adversely impacting the maximum operating speed. The switch from aluminum to copper interconnects is part of this change. Copper has the advantage over aluminum of lower resistivity and higher electromigration resistance. As a result, the switch to copper has had a major impact on the speed and operable size of microelectronic circuits.
The switch from aluminum to copper involves a variety of changes in the manufacturing process flow. Since it is difficult to etch copper, newer approaches such as “damascene” and “dual damascene” processing have been employed. Copper damascene/dual-damascene is a process in which vias and/or trenches are etched into the insulating material. Copper is then filled into the vias and/or trenches—most often by an electrochemical plating (ECP) process—and sanded back to form a planar surface with the top surface of the insulating material. This sanding back process is usually accomplished by a process such as chemical mechanical polishing (CMP). By this process, the conducting materials are only left in the vias and trenches. In the dual damascene approach, both vias and trenches are patterned into a layer of dielectric material or a stack of different dielectric materials before the copper is filled in. An advantage of this approach is that only one copper fill and CMP is necessary to form a layer of copper lines and vias that connect one layer of such lines to another layer. The dual damascene approach, however, may require a rather complex dielectric stack that includes a sequence of hard mask, low-k dielectrics, and etch stop layers. Damascene and dual damascene, multi-layer interconnect structures are known in the art. See, for example, Improvement of Thermal Stability of Via Resistance in Dual Damascene Copper Interconnection, T. Oshima, et al., IEEE (2000); and Copper Metallization for ULSI and Beyond, Shyam P. Murarka et al., in Critical Reviews in Solid State and Materials Sciences, 20(2):87–124 (1995), both of which are hereby incorporated by reference in their entirety and particularly for their discussions of the damascene and dual-damascene processes.
A significant problem for copper interconnects and vias is stress-induced void formation, especially at the bottom of vias. See, for example, Stress-Induced Voiding Under Vias Connected to Wide Cu Metal Leads, E. T. Ogawa et al., IEEE (2002), which is hereby incorporated by reference in its entirety and especially for its discussion of stress induced voiding. Stress-induced void formation at the bottom of a via may create a solid open or discontinuity in the connection between the via and the copper interconnect that can cause electrical circuits to fail. These may be termed “killer voids” as they can effectively kill a circuit's ability to operate effectively.
Copper interconnects develop severe voiding at the bottom of vias for several reasons, including the migration of vacancies or micro-voids that are attracted to the bottom of the via by stress fields. Stress fields are a product of thermodynamic and mechanical processes associated with annealing and other multi-layer circuit processing activities. Further, grain formation within the copper interconnect and/or via may further exacerbate the formation of micro-voids and discontinuities. These stress fields and grains become especially prevalent and troublesome when the copper interconnect is constrained on one or more sides by other circuit layers, such as cap layers or barrier layers. Essentially, micro-voids in the copper interconnect structure tend to migrate to and along the top surface of the interconnect, where they may escape harmlessly if that surface of the interconnect is not constrained by a layer above it. As described above, however, the damascene process places one or more layers on top of the copper interconnect, and thus the micro-voids cannot escape. The use of annealing and other processes may produce larger grain formation and additional stress fields in the copper interconnect in this constrained state. The larger grains in turn may produce further micro-voids, as the aggregation of copper into larger grains leaves more open space at the grain boundaries. The micro-voids then aggregate at the bottom of the via as they follow the stress fields. This aggregation is the basis for a killer void or discontinuity at the junction of the copper interconnect and via. The top of the via tends not to suffer such killer voids, because the stress fields there are such that the vacancies are attracted to the top of the metal interconnect (away from the via top opening). Moreover, voids at the top of vias do not generally cause a circuit failure, as there is usually enough copper in place for the current to flow out of the via.
As an example, FIG. 1 is a graphical representation of the formation of killer voids at the bottom of vias. FIG. 1 shows an inter-metal dielectric layer 106 with a via 110 through it down to an underlying metal interconnect 102. Cap or barrier layers 104, 108 are also shown. Micro-voids 112 migrate along the interface between the metal interconnect 102 and the barrier layer 104. These micro-voids 112 aggregate under the via 110 at the top surface of the metal interconnect 102, at least in part due to stress fields 114 within the metal interconnect 102. Grain boundaries 116 and the formation of larger grains during annealing and electro-chemical deposition (ECD) processing may produce additional micro-voids and increase the aggregation of micro-voids below the via. The aggregation of micro-voids 112 leads to a killer void 118, wherein the connection between the via 110 and the metal interconnect 102 is completely severed.
Attempts at fixing such stress-induced void formation have involved global changes to the manufacturing process and the structure of the circuit. Specifically, these changes have included: fine-tuning annealing conditions; changing diffusion barriers from Ti/TiN to Ta/TaN; refining electro-chemical plating conditions of the copper; and altering the stress applied around the via from inter-metal dielectrics by using a sandwich-type inter-metal dielectric. Success from using these methods has been difficult to achieve and limited in nature, and may become even more elusive as process technologies scale to smaller dimensions. Furthermore, such global changes can adversely affect the speed of the copper interconnect system by increasing either the resistance of the copper lines or their parasitic capacitances. Finally, redundant vias have been implemented to reduce the risk of an open via, but this has a substantial die size penalty and adds to the manufacturing process complexity.